The invention relates to the generation of several reference voltages in an integrated circuit, from an external voltage source and a voltage generation circuit. It can be applied especially to non-volatile memories.
Numerous integrated circuits require several reference voltages internally for low or high load current applications. In particular, non-volatile applications require multiple reference voltages for operations of reading, testing, programming or erasure. For example, to program a flash EPROM.sup.1 memory cell, it is necessary to have available a so-called programming voltage Vpp of (for example) 12 volts on the control gate of the cell, a bit line voltage of six volts applied to the drain of the cell, and a source voltage of zero volts. However, in test mode, the voltage applied to the drain of the cell will no longer be equal to six volts but will be equal to seven volts. It should therefore be possible to have both these reference voltages available. FNT .sup.1 Descriptions of flash EEPROMs may be found, for example, in Kuo et al., "A 512-kb Flash EEPROM Embedded in a 32-b Microcontroller," 27 IEEE J. SOLID-STATE CIRCUITS 574 (April 1992), and references cited therein; McConnell et al., "An Experimental 4-Mb Flash EEPROM with Sector Erase," 26 IEEE J. SOLID-STATE CIRCUITS 484ff (April 1991), and references cited therein; and Miyawaki et al., "A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories," 27 IEEE J. SOLID-STATE CIRCUITS 583ff (April 1992), and references cited therein; all of which are hereby incorporated by reference.
This need to have numerous reference voltages is aggravated by the following factors:
1) It is desirable to avoid putting any unnecessary stress on the memory cells in operational mode, and hence it is desirable to apply to the cells, at all times, the optimum voltages corresponding to each access mode; and PA1 2) In order to obtain the advantages of on-chip-self-testing, it is desirable to have all the key elements located on-chip.
It is often not practicable to provide all these reference voltages at supply terminals of the circuit: the large number of external sources entailed would be a major drawback for the user and the large number of external supply terminals is a major drawback for the manufacturer because it increases the cost of the circuit. It is therefore desirable to find solutions internal to the circuit.
A known internal approach for low-current applications is the charge pump: starting from a nominal voltage, a higher voltage is obtained by multiplier effect. Apart from the fact that this approach is not suited to high current applications, it is also necessary to have as many charge pumps as there are internal reference voltages.
The invention proposed contains a device capable of delivering a predetermined voltage level from a choice of several possible voltage levels. In one improvement, the reference voltage delivered is stable and independent of the load current of the circuit to which it is applied. This device makes it possible to give a circuit all the reference voltages necessary, by logical selection. In the invention, resistor ratios are used to obtain different voltages. Transistors are used to set up a stable reference voltage at the output, as a function of a selected resistor ratio.
Among the innovations disclosed herein is: An integrated circuit, comprising: first and second power-supply connections; first, second, and third mutually matched field-effect transistors of a first channel conductivity type; at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors; said first transistor being operatively connected between said second transistor and said first power-supply connection; said second transistor, and a respective switch in series therewith, being operatively connected between said first transistor and said second power-supply connection; said third transistor, and a respective switch in series therewith, being operatively connected between said first transistor and said second power-supply connection; and logic connected to control both said switches, and to turn on no more than one thereof; whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.
Among the innovations disclosed herein is: An integrated circuit, comprising: first and second power-supply connections; first, second, and third mutually matched field-effect transistors of a first channel conductivity type; at least one resistive bias network, connected to first and second power-supply connections, and configured to generate first, second, and third different respective constant bias voltages therefrom, and to provide said three bias voltages to gates of said three matched field-effect transistors; said first transistor having a source operatively connected to a first power-supply connection; said second transistor, and a respective switch in series therewith, being operatively connected, in series with said first transistor, between said first and second power-supply connections; said third transistor, and a respective switch in series therewith, also being operatively connected, in series with said first transistor, between said first and second power-supply connections; logic connected to control both said switches, and to turn on no more than one thereof; whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.
Among the innovations disclosed herein is: An integrated circuit, comprising: first and second power-supply connections; first, second, and third mutually matched field-effect transistors of a first channel conductivity type; at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors; said first transistor having a source operatively connected to said first power-supply connection; said second transistor, and a respective switch in series therewith, being operatively connected, in series with said first transistor, between said first and second power-supply connections; said third transistor, and a respective switch in series therewith, also being operatively connected, in series with said first transistor, between said first and second power-supply connections; logic connected to control both said switches, and to turn on no more than one thereof; whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.
Among the innovations disclosed herein is: An integrated circuit, comprising: a positive power-supply connection, and a ground connection; first, second, and third P-channel field-effect transistors, all having substantially identical geometries; at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors; said first transistor having a source operatively connected to said power-supply connection; said second transistor, and a respective switch in series therewith, being operatively connected, in series with said first transistor, between said power-supply connection and ground; at least one regulating transistor being interposed between said first and second matched transistors; said third transistor, and a respective switch in series therewith, also being operatively connected, in series with said first transistor, between said power-supply connection and ground; logic connected to control both said switches, and to turn on no more than one thereof; an N-channel output transistor connected to be controlled by a node intermediate between the channels of said first and second transistors, and accordingly to pass current from said power-supply connection to a load terminal; an additional series-connected pair of field-effect transistors, jointly connected in parallel with said output transistor, and including an additional P-channel transistor having a gate connected to the gate of said first matched transistor, and also an additional N-channel transistor having a gate connected to the gate of said regulating transistor; whereby the potential intermediate said first and second transistors provides a reference voltage which is dependent on the state of said switches, but is otherwise substantially constant.
Among the innovations disclosed herein is: A circuit for the generation of reference voltages, comprising: a first transistor placed between a positive voltage source and an output node, and having its gate biased at a first voltage; one second transistor and one third transistor connected in parallel, each being identical to said first transistor, each having its gate biased at a different respective voltage and being mounted in series with a respective switching transistor between said output node and ground; a sequence of resistors in series between the positive voltage source and the ground to deliver different bias voltages to the gates of said first, second, and transistors; logic connected and configured to make only one said switching transistor conductive at a time to generate a determined voltage level at the output of the generation stage.
Among the innovations disclosed herein is: A circuit for the generation of reference voltages according to claim 27, further having an output stage comprising: a fourth transistor capable of conducting a high current, controlled at its gate by the output of the generation stage and connected between the positive voltage source and an output of the device; a fifth transistor and a sixth transistor in series between the positive voltage source and the output of the device, the sixth transistor having a conduction electrode connected to its gate and another conduction electrode connected to the output of the device; a seventh transistor in series between the first transistor and the other transistors of the generation stage; the first transistor and the fifth transistor being identical and having their gates connected together, the sixth and seventh transistors being identical, having their gates connected together and being of the type with conduction opposite that of the first and fifth transistors.
Among the innovations disclosed herein is: An integrated circuit memory, comprising: an array of memory cells; and peripheral circuitry, including address decode logic connected to receive address bits and to access a correspondingly one of said cells; and control logic connected to receive one or more control bits and to select a mode of operation of said peripheral circuitry accordingly; reference-voltage-generating circuit, connected to receive an external voltage supply, and connected to receive bits from said control logic indicating a mode of operation, and to supply at least one reference voltage to said peripheral circuitry in dependence on said bits from said control logic; said reference-voltage-generating circuit comprising first, second, and third mutually matched field-effect transistors of a first channel conductivity type; at least one bias network, connected to provide three different constant bias voltages to the three respective gates of said transistors; said first transistor being operatively connected between said second transistor and said first power-supply connection; said second transistor, and a respective switch in series therewith, being operatively connected between said first transistor and said second power-supply connection; said third transistor, and a respective switch in series therewith, being operatively connected between said first transistor and said second power-supply connection; and logic connected to control both said switches, and to turn on no more than one thereof, in accordance with bits received from said control logic.
Among the innovations disclosed herein is: A method for generating multiple reference voltages on-chip from a single externally supplied voltage, comprising the steps of: providing first, second, and third mutually matched field-effect transistors of a first channel conductivity type; applying three different substantially constant bias voltages to the respective gates of said transistors from a voltage-dividing ladder between first and second power-supply connections; said first transistor being operatively connected between said second transistor and said first power-supply connection; selectably, when a first reference voltage is desired, connecting said second transistor, but not said third transistor, between said first transistor and said second power-supply connection; and selectably, when a second reference voltage is desired, connecting said third transistor, but not said second transistor, between said first transistor and said second power-supply connection; and connecting a node between said first and second transistors to provide a reference voltage which is substantially constant.